1. Field of the Invention
The present invention relates generally to a method for patterning semiconductors, and more particularly to a method for patterning semiconductors to reduce pitches thereof.
2. Description of the Prior Art
The need to remain competitive in cost and performance in the production of semiconductor devices has caused a continuous increase in device density of integrated circuits. As higher integration and miniaturization has been achieved in a semiconductor integrated circuit, miniaturization of a circuit pattern formed on a semiconductor wafer has also been proceeded. As a basic technique for generating the pattern, photolithography is widely known among others. Therefore, various development and improvements of the photolithography technique has been made. Smaller dimensions permit the fabrication of more devices or other integrated circuit components per unit substrate area. Closer spacing of features yields similar advantages. Design rules define the space tolerance between devices or interconnect lines so as to ensure that the devices or lines do not interact with one another in any unwanted manner. One important layout design rule that tends to determine the overall size and density of the semiconductor device is the critical dimension (CD). A critical dimension of a circuit is commonly defined as the smallest width of a line or the smallest space between two lines. Another critical design rule defines the minimum width of a given feature plus the distance to the adjacent feature edge as the minimum pitch.
Once the layout of the circuit is created, the photolithographic process utilizes an exposure tool to irradiate a layer of photoresist on the wafer through a mask to transfer the pattern on the mask to the wafer. As the critical dimensions of the layout approach the resolution limit of the lithography equipment, optical proximity effects (OPE) begin to influence the manner in which features on a mask transfer to the resist layer such that the masked and actual layout patterns begin to differ. Optical Proximity effects are known to result from optical diffraction in the projection system. The diffraction causes adjacent features to interact with one another in such a way as to produce pattern-dependent variations; the closer together features are, the more proximity effect is seen. One specific proximity effect related problem occurs when features are designed to have the same dimension, but are placed in a different proximity to other features in a layout. Features that have edges that are in close proximity to other features (referred to as in dense area with narrow pitch pattern) are more affected by proximity effects while features that have edges that are relatively isolated are less affected by proximity effects. As a result, a feature in a dense area tends to be printed differently than an isolated feature. That is to say, the narrow pitch pattern is difficult to print due to its poor aerial image contrast, especially for those pitches close to the wavelength of the light source used for exposure. Thus, patterns become increasingly smaller, and the need for improvement in resolution of patterns had been increased.
Generally, the term resolution is defined as a measure of the ability to separate closely spaced features. The resolution limit R (nm) in the photolithography technique using the reduction type projection printing is given by the following equation:
R=k1*xcex/(NA)
where xcex is a wavelength (nm) of light for use, NA is the Numerical Aperture of a lens, and k1 is a constant depending on a resist process.
As can be seen from the above equation, in order to improve the resolution limit R to obtain a finer pattern, the values of k1 and xcex should be reduced, and that of Numerical Aperture (NA) should be increased. In other words, what is required is to reduce the constant dependent on the resist process as well as to shorten the wavelength and to increase the Numerical Aperture (NA). However, enlarging the Numerical Aperture (NA) of projection system and shortening the wavelength of light source is technically difficult and costly. The implantation of costly and complex phase shift masks has significantly improved the resolution in recent years. However, for maximizing the integration of device components in the available area on the substrate to fit more components in the same area, increasing miniaturization are required. Furthermore, in the lithography process of the narrow dimension, it is usually used the photoresist material that is applied for the deep ultraviolet (DUV) process, and that the light source is usually off-axis illumination (OAI), so as to pattern the features of the masks onto wafers within the limitation of the narrow dimension. However, the process window of semiconductor devices can not be reduced without qualifications because the photoresist material of the deep ultraviolet (DUV) process or the off-axis illumination (OAI) has limitation thereof, so that working efficiency for the lithography process is reduced.
In general, the pitches could not be changes by using optical proximity correction (OPC), and further, there are limitation of the pitches in various lithography processes. For example, when the limitation of the pitch in the lithography process is 300 micrometer, the lithography process could not be performed in the condition that the limitation of the pitch is less than 300 micrometer. If it is necessary to reduce the pitch, apparatus of the lithography process will be exchanged form the narrow lines. Moreover, as narrow lines and closer pitch dimensions are needed to achieve increasingly dense packing of the components, the task of reducing proximity effect and increasing the process window of printing the narrow pitch pattern with poor aerial image contrast into the substrate becomes more and more important. Thus, the need for improvement in resolution of patterning the pitches close to the wavelength of light source without considering the limitation of an image transfer system is imperative. In accordance with the above description, a new and improved method for patterning semiconductor devices is therefore necessary, so as to raise the yield and quality of the follow-up process.
In accordance with the present invention, a method is provided for patterning semiconductor devices that substantially overcomes drawbacks of above mentioned problems raised from the conventional methods.
Accordingly, it is a main object of the present invention to provide a method for patterning semiconductor device. This invention can adjust positions of the side-lobes of the main feature""s exposure peak by changing the optical parameters of Numerical Aperture (NA) and sigma ("sgr"), so as to overlap with its neighborhood""s side-lobes. Furthermore, in this invention, the intensity of the main future""s exposure peak is about equal to the side-lobes thereof from each other by changing the transmission of the translucent mask. Therefore, the present invention can reduce the pitch so as to obtain the large process window. So, the present invention can correspond to industrial economic effect, and the present invention is appropriate for deep sub-micron technology to provide the semiconductor devices.
In accordance with the present invention, a new method for patterning semiconductor devices is disclosed. First of all, an adjusting step is performed to change a first optical parameter and a second optical parameter, so as to adjust the positions of two side-lobes of the main feature""s exposure peak and overlap with the main feature""s exposure peak and two side-lobes thereof, wherein the first optical parameter is the Numerical Aperture (NA) and the second optical parameter is the sigma ("sgr"). Afterward, a lithography process is performed by using a translucent mask to pattern the semiconductor devices, wherein the translucent mask can equalize the intensity of the main feature""s exposure peak and the side-lobes thereof from each other. Therefore, this invention can reduce the pitch to decrease the critical dimension of the semiconductor devices.